Master-slave delay locked loop (DLL) circuits may include a slave delay line that is configured to delay an input signal by a desired phase delay. As the architecture for master-slave DLL circuits moves toward lower geometries, phase delays associated with different slave delay lines, including those in different dies, may vary significantly. Accordingly, some slave delay lines may delay a received signal by an amount that is different than the desired phase delay. This difference or mismatch, referred to as static phase error, may reduce or limit performance, such as reducing timing margins to latch data.